This invention relates in general to digital data communication, and in particular to the transfer of status information related to messages transferred between two systems, such as a microprocessor system and a peripheral integrated circuit chip.
For communication between the microprocessor and a peripheral device such as a modem, a printer or a data acquisition instrument, it is often expedient for digital data to be carried in a single line connecting them. In order to do this, the parallel data from the microprocessor must be converted to a serial bit stream for transmission over the line. Similarly, serial data received from a line must be converted to parallel form before the microprocessor can process it. In typical applications, an integrated circuit peripheral chip is used to convert digital data between parallel and serial forms.
The digital message to be transferred consists of two types of information. The first type, which forms the bulk of the information, is a continuous block of data, also referred to as a frame of data. The second type is one or more words of status information containing the status of the block of data, generated either by hardware logic of the peripheral chip or the program logic of the microprocessor system. This status information is usually stored in status registers within the peripheral chip.
In the receive case, serial data enters the peripheral chip and emerges as parallel data to be written to the system memory. Should errors arise from the reception of the serial data, they would be so indicated by having one or more bits of the status registers set by the peripheral chip. After the frame of data has been transferred from the peripheral chip to the system memory, typically, the microprocessor would fetch the status information before it is overwritten by the status information on the next block of data entering the receiver.
In the transmit case, where parallel data from the system memory enters the peripheral chip and emerges as a serial data stream to an external device, the status information precedes the data block and is programmably set by the microprocessor to instruct the peripheral chip what action to take in the event of error conditions.
In either case, the status registers also carry, among other things, other information related to the format of the message such as message length, last character length and message termination type.
In high performance peripheral chips, the contiguous block of data is most efficiently transferred between the peripheral chip and the system memory under the control of a Direct Memory Access Controller (DMA). This obviates the need for the microprocessor's processing of the data transfer. However, the microprocessor's attention is still required for the transfer of the status information. Moreover, the timing is critical. In the receive case, action by the microprocessor is required to read the status information before a new message enters the peripheral chip. In the transmit case, the status information must be written before the transmission of the message itself. Furthermore, after the transmission of one message has been completed, the microprocessor must first write the status information for the next message into the status register before the transmission of the next message can begin; this again requires microprocessor intervention at critical times. The need for prompt microprocessor intervention during certain phases of the transmission process between the microprocessor system and the peripheral compromises the performance of the overall system.
Accordingly, it is a primary object of the invention to provide an improved peripheral chip which does not require microprocessor intervention for the transfer of status information.
It is another important object of the invention to have the status information transferred under the control of a DMA in such a way that status information and message information are transferred within the same block.